In recent years, with the scaling down of transistors for achieving higher integration and higher speed in LSI applications, a problem arising from signal delay of a wire has become more pronounced. As a solution, reductions in wire resistance and also capacitance between wires have been desired. Accordingly, for the purpose of reducing the capacitance between wires, a wiring layer formation technique using a low dielectric constant material having a lower dielectric constant than a silicon oxide film deposited by a conventional plasma CVD method and the like for an interlayer insulator material has been developed. Also, for the reduction of the wire resistance, a Cu wiring technique using Cu (copper) having a lower resistance than Al (aluminum) for a wire material has been developed.
On the other hand, in a semiconductor device (semiconductor chip) using the low dielectric constant film having a low dielectric constant (hereinafter, referred to as Low-k film), there is a problem that peeling occurs at an interface between the Low-k film and an underlying cap film in a chip corner portion of the semiconductor device in a process of resin-sealing the semiconductor device. In Japanese Patent Application Laid-Open Publication No. 2006-318988 (Patent Document 1) and Japanese Patent Application Laid-Open Publication No. 2006-80369 (Patent Document 2), methods for preventing such peeling are disclosed.
Japanese Patent Application Laid-Open Publication No. 2006-318988 (Patent Document 1) discloses a technique in which the peeling of the interlayer insulator from the chip corner, which is caused when the semiconductor chip is resin-sealed, is prevented by etching and removing the multi-layer interlayer insulators formed in the chip corner and then providing a resin-protection film therein.
Japanese Patent Application Laid-Open Publication No. 2006-80369 (Patent Document 2) discloses a technique in which a sacrificial pattern is provided outside a guard ring in the chip corner portion, thereby preventing the peeling of the interlayer insulator from the chip corner to progress inside the guard ring by the sacrificial pattern in a thermal cycle test after resin-sealing the semiconductor device.